As scaling continues to ever smaller feature sizes, integrated circuit (IC) reliability is an increasing concern in IC fabrication technology. The impact of trace interconnect failure mechanisms on device performance and reliability demand much more from integration schemes, interconnect materials, and processes. An optimal low-k dielectric material and its related deposition, pattern lithography, etching and cleaning are required to form dual-damascene interconnect patterns. A hard-mask scheme approach of interconnects-patterning wafer fabrication is the ability to transfer patterns into under layers with tightest optimal dimension control.
As technology nodes advance to nanotechnology, metal hard-mask materials such as TiN are used to gain better etching/removal selectivity, better pattern retention and profile control to the low-k materials during the pattern etching process.
Formulations have been developed to pullback or remove these types of metal hard-masks from substrates.
The following patents are representatives.
US2013/0157472 describes the formulations comprising Cl−, or Br− an oxidizer and potentially a Cu corrosion inhibitor to clean substrates containing low-k dielectric and Cu and to etch a TiN or TiNxOy hardmask and tungsten. The formulation typically contains 6% hydrogen peroxide as the oxidizer and diglycolamine to adjust the pH to >7.
US 2009/0131295 A1 describes the removal of hard mask residues (typically TiF containing) after plasma etch from TiN at a pH of 1-8 using acidic or basic fluoride or bifluoride.
U.S. Pat. No. 7,479,474 B2 describes cleaning formulations comprising H2SiF6 or HBF4 to reduce oxide etch in a substrate comprising low-K dielectric.
WO 2013/101907 A1 describes formulations comprising etchants including hexafluorosilicic acid and hexafluorotitanate, at least one oxidant including high valent metals, peroxide or high oxidation state species and at least one solvent.